1. Field of the Invention
This invention relates to a programmed digital data processing system including a watch-dog circuit arrangement, which arrangement comprises timer means coupled to a reset signal input, said arrangement being arranged to generate an output signal should the time interval between successive resets of said timer means exceed a predetermined length, to generate a further signal at intervals which do not exceed said predetermined length, and to also generate said output signal should a reset signal be supplied to said reset signal input while the further signal is absent. The system is programmed to supply a reset signal to said reset signal input, and thereby reset the timer means, during each occurrence of said further signal; and to respond to said output signal by assuming a predetermined operating state.
2. Description of the Related Art
A system of the above kind is disclosed in GB-A-2 065 939.
Watch-dog circuit arrangements in general are well-known, and serve to monitor the correct implementation of a data processing system program. The timer means may, for example, take the form of a continuously clocked counter which produces an output signal should the count therein reach a predetermined value or its capacity is exceeded, the counter having a reset input at which a reset signal applied thereto results in the counter contents being set to zero. The data processing system may comprise a suitably programmed microcomputer, a single bit-line of one of the output ports of which is coupled to the reset input of the counter. The computer is programmed in such a way that a signal which resets the counter is periodically applied to the signal bit-line at such a rate that the counter is always reset before its contents reach the value at which it would generate the output signal. Thus in normal operation the counter never produces an output signal. If, however, the implementation of the program should cease for some reason, resulting in the resetting of the counter also ceasing, then the counter contents will eventually reach said predetermined value. The resulting output signal may, for example, be applied to a general reset input of the microcomputer, so that the microcomputer is itself reset under these circumstances. A similar result is obtained if the microcomputer should incorrectly enter a program loop which does not include a step entailing the application of a reset signal to the counter, or which does include such a step but in which this step is repeated insufficiently frequently to prevent the counter contents reaching said value.
The aforesaid patent specification GB-A-2 065 939 discloses an elaboration of such a basic circuit arrangement which is arranged to also generate an output signal to reset the microcomputer should the time interval between successive occurrences of the timer reset signals be less than a predetermined value, thereby also resetting the microcomputer if it should incorrectly enter a short program loop in which steps resulting in the application of reset signals to the timer occur too frequently. To this end the reset signal input of the microcomputer, in addition to being coupled to the reset input of the counter, is coupled to the output of the watch-dog arrangement at which the output signal occurs via an AND-function gate the other input of which is fed from the output of a decoder. The decoder is fed from selected stages of the counter, so that as long as the counter contents lie within a predetermined range (corresponding to the duration of a predetermined time interval after the occurrence of the immediately preceding timer reset signal) the decoder produces an output signal (the aforesaid further signal) which inhibits the gate.
Obviously, such a system has to be programmed to supply reset signals to the reset signal input of the microcomputer during normal operation at intervals which are such that each reset signal occurs within the predetermined time interval after the occurrence of the last such reset signal. This is fairly easy to arrange if the system program consists of a single loop the various steps of which, and only these steps, are performed for each cycle round the loop. However, many programs do not take this simple form. For example, routines may or may not be called, and/or different branches may be taken in dependence upon current conditions. In such cases it can be difficult and time-consuming for a programmer to ensure that timer reset signals are always generated in normal operation at the correct rate. It is an object of the invention to mitigate this disadvantage.